Computer speeds continue to become faster. A fast clock signal is required for fast data processing. Harmonic components are exhibited by a high speed clock signal. Electromagnetic interference (EMI), which is harmful to the human body, is generated by the harmonic components. EMI in a system has been reduced by shielding or using capacitance. However, there are limitations on reducing EMI in a system by shielding or using capacitance.
Most of the EMI in a computer system is generated in a clock generating portion that generates the high speed clock signal. In other words, EMI is generated in a high speed clock signal due to harmonics. Recently, techniques for reducing EMI by lowering the energy level of harmonics have been developed. In general, a phase locked loop (PLL) is used to generate a clock signal, and the PLL generates a modulated clock signal, which is known as a spread spectrum signal, to reduce the energy level of harmonics contained in the clock signal. FIG. 9 is a block diagram schematically illustrating a PLL according to the Background Art.
As described above, a method for generating a modulated clock signal in a PLL circuit includes a phase modulation method and a frequency modulation method. A Sigma Delta method is used as the phase modulation method. The Sigma Delta method is a technique which reduces the energy level of EMI by modulating the phase difference between a reference input frequency and a feedback frequency by using a sigma delta modulating block that finely controls current via a charge pump block in the PLL. The frequency modulation method is a technique which reduces the energy level of EMI by utilizing the phase lock range of the PLL circuit via a multiple counter or read-only memory (ROM) used to feed back a frequency generated by a voltage-controlled oscillator (VCO) in the PLL circuit.
However, each of the spread spectrum clock signal generators using the Sigma Delta modulation method or the frequency modulation method is designed to reduce the energy level of a certain frequency and each has a problem that variation in its characteristics can be large. Furthermore, since the size of physical data is large and it is difficult to adjust timing between peripheral blocks when controlling the PLL circuit, malfunction in the PLL circuit can easily occur.